Prior art semiconductor technology (e.g., 40 nanometer (nm), 14 nm and beyond) currently has most gate (CB) contacts disposed on a portion of the gate structure that is located outside of any active (Rx) region and over an isolation region such as a shallow trench isolation (STI) region, a deep trench isolation region or the like. This is done to prevent the high risk of electrically shorting to source/drain (CA) contacts or to the underlying trench silicide (TS) layers.
The possibility of CB contacts shorting to the TS layers is especially problematic. This is due to the fact that the TS layers extend longitudinally across an entire Rx region in order to ensure proper electrical contact with the source/drains (S/D) of FinFETs in an array of fins even under worst case misalignment conditions. Therefore, even though the CA contacts can be located in a localized area of the Rx region sufficiently distant from the CB contact to prevent shorts, the TS layers cannot.
In prior art 10 nm technology and beyond, self-aligned contact (SAC) nitride caps over the gate electrode metal are utilized to prevent shorting between CA contacts and the gate metal. The SAC caps are composed of a single material, typically silicon nitride (SiN), that generally has the same or similar material composition as the gate spacers over which the SAC caps are disposed. Between the gate spacers and SAC cap, the gate metal is completely isolated from the TS regions. With such caps, it is possible to do a deep TS recess below the level of the gate metal in an attempt to avoid shorting to CB contacts potentially disposed in the Rx region.
Problematically though, there are limits as to how deep the TS layer can be recessed without unacceptably increasing the electrical resistance through the TS layer. Therefore, even with such a deep TS layer recess, the CB contacts disposed over the gates become too close to the recessed TS to be reliably manufactured.
Placing the CB contacts outside of the Rx region is a detriment to scaling, especially for the 10 nm technology nodes and beyond. Additionally, CB contacts disposed over the isolation regions have additional design requirements that become more problematic with down scaling. For example, the CB contacts over isolation regions must always be located between two Rx regions, must have a minimum spacing between the CB contact and the fins and the TS regions, and the like.
Accordingly, there is a need for a method and apparatus that enables the placement of CB contacts inside of Rx regions of semiconductor structures. Moreover, there is need for such method and apparatus to be reliably manufacturable.